Calculator system having a constant memory

ABSTRACT

Disclosed is a portable calculator system featuring a constant memory in addition to an instruction memory. The constant memory is preferably implemented as a virtual ground ROM which is addressed by the same signal which addresses the instruction memory for executing an unconditional branch. A keyboard storage register responsive to keyboard inputs provide memory address to the constant memory in a multi-digit command word having first and second sets of digits. The second set of digits represents the constant memory address which is executed only if the first set of digits so command. The second set of digits also represent a chip select signal for enabling only the specific memory on a specific memory chip if a multi-chip system is utilized.

United States Patent Cochran et al.

CONSTANT MEMORY CALCULATOR SYSTEM HAVING A [75] Inventors: Michael J.Cochran, Richardson;

Charles P. Grant, Jr., Dallas, both of Tex.

[73] Assignee: Texas Instruments, Incorporated,

Dallas, "Ex.

[22] Filed: Sept. 13, 1973 [21] Appl No.: 397,181

[52] US. Cl H 235/156; 340/172.5

[51] Int. Cl. G06F 9/10 [58] Field of Search 235/156, 159, l60, 164;

[56] References Cited UNITED STATES PATENTS 3,720,820 3/l973 Cochran235/156 3,760,171 9/[973 An Wang ct al l v l v 235/156 3,775,756 11/1973Balscr 340/1725 3.800.129 3/1974 Umstattd 235/156 R EG. SELECT Sept. 9,1975 [57] ABSTRACT Disclosed is a portable calculator system featuring aconstant memory in addition to an instruction memory. The constantmemory is preferably implemented as a virtual ground ROM which isaddressed by the same signal which addresses the instruction memory forexecuting an unconditional branch. A keyboard storage registerresponsive to keyboard inputs provide memory address to the constantmemory in a multidigit command word having first and second sets ofdigits. The second set of digits represents the constant memory addresswhich is executed only if the first set of digits so command. The secondset of digits also represent a chip select signal for enablingonly thespecific memory on a specific memory chip if a multichip system isutilized.

12 Claims, 80 Drawing Figures ROM I ADDR ESS REG. l

Hlllllllll HOLDING REG.

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o X, *1 *4 U S 8 2? CONSTANT m 1 ROM 5 ADDRESS 1 HI I J CONST (It- 131/0 3/ 37 CONTROL i/o ...1/o

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PATENTEU 9|975 3,904,862

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I ARITHM ETIC CHIP Ill'l' I' SEGMENT DRIVERS DIGIT DR IV ERS "K" LINESKEYBOARD PATENTEI] SEP 9 i975 SHEET mHZNA &

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PATENTEU 9W5 3,904,862

(brlalngch J b ri nih Fig 3 MO Flag Opfi'ration I Branch of I11 M1 AllMask ll C0nditi0n=1 (md) M2 DPT MSB M3 DPT 1 1 MA DPT c I M5 LLSD 1 (me)M6 EXP MSB M7 EXP 1 M8 KEYBOARD OPERATIONS I M9 MANT 9 (mb) M10 WAITOPERATIONS M11 MLSD 5 M12 MAEX 1 LSB M13 MLSD 1 8 (ma) Ml L MMSD 1 M15MAEX 1 I I R0 A N 7 R1 B+N (Rd) R2 c N MSB R3 O+N RLL Shift A RelativeR5 Shift B n h (RC) R6 Shift 0 Address 7 Shift D I R8 A+B R9 SIB ly 3 Im R11 AIB I21 I R12 AEConstant' 11 R13 NO-OP (Ra) Rl L C+ Constant LSBR15 R5-Adder (Mask LSD) I J =O=add=shift left 12 =1:sub=shift right 7cTO=Z-A LSB T1=Out ut 1/0 J I E2=A-R O =O=INCREMENT 1 3 PB (EFFECTIVE FOR=l=DECREMENT 2 153-43 WHOLE INSTRUC- TION CYCLE WITH I Y5=YTD ANY DIGITMASK) O 7=A-E Ea. LSB

PATENTEU 9 3975 7% 9 O4, 8 5

SHEET 7 The following 8 bits effective only if flag Operations 7 (fmd)MSB 16 The following 8 bits effective Generate Fla'gMaSK only ifKeyboard operations when these LL bite equal the encoded state I bltS=O=SCAN KYBD (NOTE: ENCODED STATE TIMES ARE +2 FROM ACTUAL STATES) A=l=KT (fma) LSB 6 =O=KS The following bits (flagops) effective onlyduring flagmask I except f E 115 5 =O=KR O TEST FLAG A E Q 1 TEST FLAG B2 SET FLAG A I I 3 SET FLAG B 2 =O=KP (fd) a ZERO FLAG A I MSB 5 ZEROFLAG B 11 6 INVERT FLAG A C & 7' INVER'I FLAG B IO 8 EXCH. FLAG A B=O=KN (fb) 9 COMPARE FLAG A B 10 SET FLAG KR 11 ZERO FLAG KR F/g, LSB 12COPY FLAG E-A 13 COPY FLAG A-B l L REG 5-FLAG A S0 s3 1" 15 REG 5'FLAG BS0 S3 F lg 50 PAIEM I M1 5 9 W5 3 9 04, 8 5'2 I STATE TIME I Fig, 60

SHEET 12 Fj g 5 Fig. 8b2 Fig.8b3 Fig. 8h4 Fig. 8b5

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Fig. 8C5 Fig. 8C6 g. 8c? Fig. 8C8

Fig. 8d1 Fig. SdZ Fig. Bd3

Fig. 8d4 Fig. 8d5 Fig. 8d6

PATENTEBSEP 91975 904, 862

SHEET 14 Fig. 8b.?

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1. A portable electronic calculator system implemented on at least onesemiconductor chip comprising in combination: a. means for generating acommand signal containing first and second sets of digits, said firstset representing internal operating states of the calculator system andsaid second set representing a memory address conditioned upon a digitof said first set; b. an instruction memory for storing a large numberof instruction words and providing a selected one in response to saidcommand signal; and c. constant memory means also responsive to saidcommand signal for generating a multi-digit, multi-bit constant forexecution in said calculator system.
 2. The calculator system accordingto claim 1 wherein said constant memory means includes constant decodingmeans including a register for storing a selected subset of said secondset and generating a first signal representing whether or not saidconstant memory means have been addressed and for generating a secondsignal representing the location of the particular constant in saidconstant memory which is addressed.
 3. The calculator system accordingto claim 2 wherein the constant memory means further comprise: (c) (i)means responsive to an instruction word from said instruction memory forgenerating a recall signal; and (ii) means responsive to said firstsignal and said recall signal for generating a gating signal for gatingsaid subset of said second signal to said constant memory as an address.4. The calculator system according to claim 3 wherein: a. saidinstruction memory is a sequentially addressed memory having columnlines sequentially strobed by subcycle times of said calculator system;and b. said constant memory has rows strobed by said subcycle times. 5.The calculator system according to claim 4 wherein said constant memoryis a read-only-memory.
 6. The calculator system according to claim 5wherein said read-only-memory is virtually grounded.
 7. The calculatorsystem according to claim 6 wherein said virtual ground read-only-memorycomprises single transistor memory cells having row transistors withcommonly connected gates and column transistors having commonlyconnected sources and commonly connected drains, said rows of gatesstrobed by said subcycle times.
 8. The calculator system according toclaim 7 wherein the constant memory means further include addressingmeans which are responsive to said subset of said second set and to saidrecall signal for coupling a selected column line of a selected cell tocircuit ground and for connecting said cell to an output line.
 9. Thecalculator system according to claim 8 wherein said constant memory hasonly one output line per bit of the constant word.
 10. The calculatorsystem according to claim 9 and further including precharge meansresponsive to a phase of said subcycle time for selectively prechargingeach of said column lines including said output lines.
 11. Thecalculator system according to claim 9 wherein circuit ground is coupledto said constant memory through a gating means responsive to aparticular subcycle time.
 12. The calculator system according to claim 1wherein said means for generating a command signal includes storagemeans responsive to keyboard inputs to the calculator system and tocycle times of the system for generating said second set.